Two register parallel binary adder/subtractor

ABSTRACT

Binary arithmetic member for adding and subtracting binary numbers, in which the input register and the accumulator have connected between them a control-device comprising a sensing circuit for sensing the least significant bit place, where the binary number to be added or subtracted has a bit value &#39;&#39;&#39;&#39;1,&#39;&#39;&#39;&#39; whose outputs corresponding to the respective bit places of the binary number are connected to the corresponding inputs of the accumulator so that under the control of a starting pulse that bistable flip-flop of the accumulator changes its state which ordinally corresponds to said least significant bit place where the binary number to be added or subtracted has a bit value &#39;&#39;&#39;&#39;1,&#39;&#39;&#39;&#39; said control-device comprising furthermore a gate circuit which, together with the sensing circuit, satisfies a given logical equation, so that a simple arithmetic member is obtained. A special device is provided for adding to or subtracting from the result in the accumulator an additional binary number 1 when the accumulator passes the zero position (FIGS. 2, 2a, 2b, 2c, 2d).

United States Patent De Boer [451 July 1 1, 1972 [54] TWO REGISTER PARALLEL BINARY ADDER/SUBTRACTOR Primary Examiner-Eugene G. Botz Assistant Examiner-David H. Halzahn [72] Inventor: Eeltie De Boer, Emmasmgel, Erndhoven, A"omey Frank Trifafi Netherlands [73] Assignee: U.S. Philips Corporation, New York, NY. ABSTRACT [22] Filed: June 4, 1970 Binary arithmetic member for adding and subtracting binary numbers, in which the input register and the accumulator have [21] Appl' connected between them a control-device comprising a sensing circuit for sensing the least significant bit place, where 30 F i Application p m n the binary number to be added or subtracted has a bit value 1," whose outputs corresponding to the respective bit places June 7, 1969 Netherlands ..69087l0 of the binary number are connected to the corresponding puts of the accumulator so that under the control of a starting [52] U.S. Cl ..235/l75 pulse that bistable flipflop of the accumulator changes its [51] W606i 7/50 state which ordinally corresponds to said least significant bit F eld 0 place where the number to be added or subtracted has a bit value 1," said control-device comprising furthermore a [56] References Cited gate circuit which, together with the sensing circuit, satisfies a UNITED STATES PATENTS given logical equation, so that a simple arithmetic member is obtained. A special device IS provided for adding to or sub- 3.290,494 12/1966 schnel'ergel' a] 175 tracting from the result in the accumulator an additional bi- 3,320,410 5/ 1967 Bane a] 235/175 nary number 1 when the accumulator passes the zero position 3,375,358 3/1968 Franck 235/175 (FIGS 2, 2 2 2 2d 3,417,236 12/1968 Utley ...235/175 3,488,481 1/1970 Franck ..235/175 7 Claim, 9 Drawing figures TT C T Q T:

LE 1. i i 2 CJ V r-, 1T i (ACCUMULATOR E 1 o c1 5 nn J. I l I i 821E? A B A 8 AB; AA;., AB. ,TI I

A 0 a o a A 1 AA; T3 LB, AA, AA SENSING 6A8! CIRCU'T I cl R c n i i I I -g;r-- F e+r-ri/+rhF 1 1 2 2 a r u ut n n t a 2 2 l I n 1 ,INPUT REGISTER 2 P I r v J a -c, c, c c

3,676,657 SHEET 10F 5' o fiilillliillllu fllllliv,

PATENTEDJuL 1 1 1972 INVENTOR. EELTJE DE BOER AGEN PATENTED UL 1 1 m2 SHEET 3 [IF 5 0 mw m INVENTOR. EELTJE DE BOER AGENT PATENTEDJUL 1 1 m2 SHEET t 0F 5 INVENTOR. EELTJE DE BOER' AGENT TWO REGISTER PARALLEL BINARY ADDER/SUBTRACT OR I The invention relates to arithmetic units and more specifically to a binary adding arithmetic member comprising an accumulator in which a first binary number can be received, the accumulator consisting of a plurality of bistable flip-flops having states characterized by and l, and an input register in which a second binary number can be received. A controldevice is provided having inputs to which are connected the outputs of the accumulator and the outputs of the input register, the control-device producing control-signals for the adjustment of an adding result in the accumulator. The accumulator is controlled so that in order of succession those bistable flip-flops change their states at the consecutive bit places of the accumulator for which, on the basis of a O-to-l changeover of a preceding bistable flip-flop, a next-following corresponding bit place of the second binary number has a bit value 1 and for which, on the basis of a l-to-O-change-over of a preceding bistable flip-flop a next-following, corresponding bit place of the second binary number has a bit value 0.

Binary adding arithmetic members are known wherein the adding process is chosen so that only those bistable flip-flops of the accumulator change their states which have, in fact, to

do so in order to form the result (see Richards: Arithmetic Operations in digital Computers, 1957, pages 110, 111 and 124). Many practical embodiments have been designed on the basis of said adding process in order to obtain adding arithmetic members operating at maximum speed, while the number of components remained within reasonable limits. In the present development of integrated circuits it has become apparent that parts of given devices such as adding arithmetic members operate with such speeds that the addition times of such an arithmetic member are well within the limits of the operation times of the devices surrounding the arithmetic member and co-operating therewith, for example a memory store. At present arithmetic members are being used in a growing number of fields, particularly where these members co-operate more or less directly with memory stores, which are comparatively cheap and hence comparatively slow so that a high arithmetic speed cannot be effectively utilized. In this respect an adding arithmetic member is sometimes evalued in the first place not for its maximum speed of operation but rather for its complexity and flexibility. The invention therefore has for its object to provide a binary adding arithmetic member which is simple in construction and easy to handle and which has a given time of operation determined especially by the use of integrated subassemblies and being of the order of magnitude of that of the devices, for example, cheaper memory media, surrounding the arithmetic me nber.

For the successive control of the binary stages said known device requires a counter giving off at given instants an arithmetic instruction in order of succession for each of the stages. The arithmetic member according to the invention performs the adding operation fully automatically without the need for such a counter. For this purpose the binary adding and subtracting arithmetic member according to the invention is characterized in that the control-device comprises a sensing circuit for sensing the least significant bit place where said second binary number has a value 1. The outputs of the control device corresponding to the respective bit places ofthe binary number are connected to the corresponding inputs of the accumulator so that by a starting-pulse instruction under the control of the sensing circuit that bistable flip-flop of the accumulator which corresponds ordinally to said least significant bit place where the second binary number has a bit value 1 changes its state. The control-device comprises a gate circuit which together with said sensing circuit satisfies the following logical equation, so that a control-signal is applied to an output 1, for controlling an i"' bistable flip-flop of the accumula- A l?! 1. Ci i-J 3E wherein c,,, are bit values of the ordinally consecutive bit places of the second binary number and the A A, and A B, represent the l-to-O changes of state of the complementary outputs (A,, B of a bistable flip-flop (FE) of the accumulator.

- This arithmetic member enables not only addition but also subtraction. Starting from a O-state subtracting is equal to adding, the result having a negative sign. The binary adding arithmetic member according to the invention may be extended in a simple manner for non-ordinal addition and sub traction of binary members. The arithmetic member according to the invention is in this respect characterized in that the bistable flip-flops of the accumulator are provided with addition-subtraction.control. In the event of subtraction A A, in said logical equation can be replaced by A B; and A B, by A A The arithmetic member further includes a signalling device for assessing zero passage of the accumulator as a whole, the signalling device including a bistable sign flip-flop which supplies an additional binary number 1 to be subtracted from the result in the accumulator, when the accumulator passes through zero from positive to negative due to the subtraction, whereas the bistable sign flip-flop provides a binary number i additionally to be added to the result in the accumulator, when the accumulator passes through zero from negative to positive due to an addition. Consequently, the arithmetic time is twice the normal value when the accumulator passes through the 0-position. Where given sequences of binary numbers have to be added and subtracted in arbitrary order, the accumulator may pass many times through 0. if, as stated above, an additional 1 has to be added to or subtracted from the result of each passage of the accumulator through zero, the total arithmetic time required for such a sequence of additions and subtractions may be considerably prolonged. For mitigating this drawback the addition and subtraction arithmetic member according to the invention is characterized in that the signalling device comprises an additional bistable flip-flop, which retains the state of the bistable sign flip-flop at the beginning of a series of additions and subtractions, the addition or subtraction of an additional binary number 1 being performed only when after said series the state of the bistable flip-flop of the sign differs from the state of said additional bistable flip-flop.

7 It should be noted that by the arrangement according to the I invention a subtraction can also be performed on the principle I of adding the number to be subtractedin a complementary form. In this case, however, at each subtraction that occurs without the accumulator passing from positive to negative through zero, an additional 1 is added. For this purpose an arithmetic member according to the invention is characterized "in that the input register is provided with a gate circuit by which, in subtracting, the second binary number is fed in the inverted form in the arithmetic member so that in the logical equation c can be replaced by (T and E. The arithmetic member includes a signalling device supplying an additional l to be added to the result in the accumulator at each subtraction and at the passage of the accumulator through zero from .negative to positive.

Thus the average arithmetic time is prolonged by a factor 2. l-lowever, in the case of an arbitrary order of additions and tions and/or subtractions, which total number has to be added in addition to the final result in order to obtain a correct final result. A further arithmetic member embodying the invention is characterized in that signalling device further includes a 2- way counter which registers the number of times of subtractions and passages of the accumulator through zero from negative to positive in one series of additions and subtractions, the position of said 2-way counter being added to the result in the accumulator after one such series.

It appears that the addition and subtraction member in accordance with the invention is especially suitable for reducing the arithmetic time particularly by its structure. For fixing the arithmetic time the least favorable case has to be taken into account in which all bistable flip-flops of the accumulator change their states. In practice this will occur rarely.

The arithmetic time for each adding and subtracting operation is usually shorter and is mainly determined by the number of bistable flipflops having to change their states. It is always certain that those bistable flip-flops will not change their states for which the consecutive bit places of the second binary number have Os from the least significant bit place. The first change is only possible from said least significant bit place where the second binary number has a bit value 1. Further changes may occur throughout the length of the accumulator, but this is not always true. When the last change can be sensed, this means a high average economy in arithmetic time. In order to achieve the aforesaid increase in operational time of the arithmetic member the binary addition member is in this respect characterized in that the output of the controldevice for the control-signal (T,,., of the last stage of the control-device and the output of the control-device for the signal (A B, 11,, E 5,) produced in the 1st stage due to the change-over of an ordinally higher preceding bistable flip-lop are connected to a starting pulse generator (P, Q,, 0,) which provides a starting pulse (St,) after the appearance of one of said two signals.

In the case of an arbitrary order of additions and subtractions it should be ensured at the passage of the accumulator through zero that any control-signal from the last stage of the control-device must not result in a new state. First the whole arithmetic process has to be completed (the addition or subtraction of the additional 1 at the occurrence of an endaround-carry). According to this aspect a further binary adding and subtracting arithmetic member embodying the invention is characterized in that a number of AND-gates (l7, 20) is provided. To each input of such AND-gates are connected an output of the bistable sign flip-flop, an adding or subtracting instruction line and the more or less delayedcontrol-signal (T,,,,) of the last stage of the control-device, so that the control-signal (T of the last stage of control-device can attain the starting pulse generator (P, Q,, Q only if required after the passage of the accumulator through zero, when the adding or subtracting process is completed.

The invention will be described hereinafter more fully with reference to the drawing.

In the drawing:

FIG. 1 shows schematically a binary addition arithmetic member in accordance with the invention.

FIG. 2 and FIGS. 2a to 2d show an embodiment of a binary adding and subtracting arithmetic member for adding and subtracting binary numbers in arbitrary order in accordance with the invention.

FIG. 3 shows a variant of the component (S) of FIG. 2b.

FIGS. 4 and 5 show alternate logic schemes for the arithmetic member adapted to operate with higher speed.

It should be noted that corresponding parts are designated in the Figures by the same references.

FIG. 1 shows schematically a binary adding arithmetic member in accordance with the invention. Reference numeral I designates the accumulator comprising a portion la having bistable flip-flops FF FF ..FF,, and a portion lb having bistable flip-flops FF,, FF The latter group of flip-flops of portion lb serve for processing the overflow .of the preceding portion la. If m binary numbers with n bits are added, the number of required bistable flip-flops is n p, where p originates from 2' e m 2", for example, if m 100, p is 7, so that, for example, if n 6, the total number of flip-flops N n p 13. Reference numeral 2 designates the input register having in this case n+1 bistable flip-flops 2, 2',....2". The input register supplies the second binary number c 0,, c ...c,, and the complement thereof 6,, E,,...Z,,. Reference numeral 3 designates the control-device comprising the sensing circuit 4 and the gate circuit 5. The sensing device 4 receives in the groups indicated the signals c 5,, 8,; E 6,, c,;... E Z,... Z, q; E 5, E,, c,,. The sensing circuit 4 determines at which least significant bit plate i of the second binary number c 0,, a bit value 1 is present. Thus an output T,, which is in addition an output of the control device 3, has a control-signal for the bistable flip-flop concerned FF, of the accumulator l. The

gate circuit 5 comprises gates to which are transmitted the signal variations A A A B A A,, A B A A,, A B,; A A A B,, A A A B, appearing at the outputs of the respective bistable flip-flops FF,,, FF,, FF,,, for example, by means of for example differentiating networks D in the case of changeover of state. The gate circuit 5 also receives the signals 0,, Z,; c,,, E The outputs of the gate circuit 5 in conjunction with the outputs of the sensing circuit 4 form the outputs T,, T T,, T of the control-device 3. An output T, conveys a control-signal for a corresponding bistable flip-flop FF,, if: T,=m+ -c, CH Z, AA, c c, -c,+... +AA, 'c, Z, +AAF1 C|+ABO'E1 .NFFI C i'AB ---C 1 C l... B52 FF! C+A BFI C In this logical equation a represents the and-function and represents the or-function.

+ a i 0 15 5 4 W 2 3 W 2 3 1 5 3 4 i s- It should be noted that a construction completely formed by Nand or Nor elements is taken into consideration, but constructions with andor or-functions and large-scale integration are also imaginable. The logical function may then be different with respect to the complementary sign above each term of the equation for T,; for example, they may be no complements but the non-complementary values. This type of variants is explicitly associated with the domain of the invention because there are no essential differences.

The operation of the arrangement shown in FIG. 1 is best explained with reference to an example.

It is assumed that the accumulator has a binary number A A A.,, A A A,, A 010011, this is to say in the complementary form; B B,, B B B B,, B,,= I01 100. These numbers A and B are consequently the states at the outputs and the complementary outputs respectively of six bistable flipflops FP FF.,, FF FF FF,, FF

It is assumed that a binary number c 0,, c c e c,, c,,

100110 has to be added. Be it furthermore assumed that a A A, or A B, is produced at a change of state from 1 to 0 in a bistable flip-flop FF,. Consequently:

A=010011 B=10ll00 C=l00ll0 Newstate A= 111001 B=0001l0 The result is formed as follows: The sensing circuit 4 senses a bit value for 0,, so that T, obtains a control-signal by which FF, is changed over. F F does not change its state. FF, was in the state A, l or B, =0 respectively; this becomes A, =0, B, I. As a result the l-to-O change-over at the A, output appears as a A A, signal at the output of the differentiating network D. This A A, passes to the gate circuit 5 where it produces a next-following control at the output T, in conjunction with that c, for which the number has a bit value 0. Thus T, AA,-c,-Z, (for example by and-gates) is satisfied (A, l, l and c 0 or I, 1 so that T, provides a control-signal for the change-over of FF,,. FF, is thus skipped. FF, was in state A,,= 0 or B l and this becomes A l, B,,=O. As a result the difierentiating network D passes to output B, a signal: A B I. This A B 1 passes to the gate circuit 5, where together with that c, for which the number c has a bitvalue 1 it provides a next-following control-signal at output T,. Thus T AB 'cfl-c is satisfied so that T, provides a controlsignal for the change-over of FF,,. FF, is thus skipped. Then the addition is completed.

For a better understanding of said gate circuit it will be described in detail in a further example, FIG. 2 and FIGS. 2a to 2d illustrate a detailed embodiment of a binary adding and subtracting arithmetic member for adding and subtracting binary numbers in an arbitrary order in accordance with the invention. FIG. 2 illustrates how FIGS. 2a to 2d are associated.

The accumulator portion 1a, the sensing circuit 4 and the gate circuit 5 are shown in detail in FIG. 20. FIG. 2b shows the accumulator portion lb with a bistable sign flip-flop. FIG. shows a read gate circuit. FIG. 2d shows an input register circuit.

The accumulator portion 1a comprises the bistable flip-flop F F,,, FF,,,. These flip-flops comprise the outputs A,,, B A,, B, respectively etc. These outputs A,, B, are each connected via differentiating networks D, for example, having a resistor R and a capacitor C, to two Nands 6, 8 and 5A, 7 respectively. The Nands 5 and 6 are furthermore connected to a line Ad which may convey an adding instruction. The Nands 7 and 8 are connected to a line Sbt, which may convey a subtracting instruction. In the case of addition and at a 1-to-0 change-over of the output A, of a bistable flip-flop FF, a signal 0 appears at the output of Nand 6. This signal 0 provides after an inverter I, a signal A A, 1. In the event of addition and at a l-to-O change-over of the output B, of the output B, of a bistable flipflop FF, a signal appears at the output of Nand 5A. This signal 0 provides after an inverter 1, a signal A B, 1. In the case of subtraction and at a 1-to-0 change-over of the output A, of FF, a signal 0 appears at the output of Nand 8. This signal provides after the inverter I, a signal A A, 1. In the case of subtraction and at a l-to-O change-over of the output B, of FF, a signal 0 appears at the output of Nand 7. After the inverter I, this signal provides a signal A B, 1. At the bistable flip-flops these signals are indicated by A A,/ A B, (at the right) and A B,/ A A, respectively (at the left). Consequently, an addition and a subtraction are distinguished from one another in the control of the accumulator.

The sensing circuit is formed here by Nands 30, 31, 32 310, to which are applied the aforesaid groups c 6 c,; E 6,, c,; 6,, E, c,, signals of the second binary number 0.

The gate circuit comprises Nands 411, 412, 413 and 414 for processing the signals A A,,/ A B A B,,/ AA,,, c, and E}; the outputs of Nand 31 of the sensing circuit, of Nand 412 or 414 provide the signal T,, that is to say for an addition: T, =a AA,,T, ABE, and for a subtraction T, =Efi+ A8 2, m. In this example the or) function is performed by a through-connection. In dependence upon the integrated circuits employed this is possible or intermediate elements (e.g., an or-gate) have to be included. The gate circuit comprises in this case Nands 421, 422, 428 for processing the signals AA,/ AB,, AB,/ AA,, 0 and F, and the signals (A A,,/ A B,,)-c, and (AB,,/ AA,,)E, (produced after inversion in the inverter I). The outputs of Nand 32 of the sensing circuit, of Nand 423 or 424, of Nand 427 or 428 provide the signal T that is to say for an addition: 2 W EH 2 i -2 AB,,-E,-c AB,c and for a subtraction:

This is continued up to and including the last stage of the accumulator portion 111, that is to say T,,, is obtained from Nand 310 or 4103 or 4104 or 4107 or 4108. A control-signal T,, for the accumulator portion 1b is produced either at the output of Nand 4101 or 4102 or at the output A A,,/A 13, of the bistable flip-flop FF (an output A B,,,/A A,,, of this flip-flop is not used). The operation of said arrangement will be apparent also from the operation described above of the arrangement shown in FIG. 1. The aspects involved in the arbitrary order of additions and subtractions will be dealt with hereinafter. Moreover, the element 0,, and 0,, and Nand P will be explained. The device starts an arithmetic process by a starting instruction from line St,. FIG. 2b shows the accumulator portion 1b constructed as a two-way counter with control across the lines Ad and Sbt. The accumulator portion lb is followed for the arbitrary order of additions and subtractions by a signalling device S for assessing the passage of the accumulator through zero. The signalling device S comprises in this case a bistable sign flip-flop FF which is controlled from the last stage of the accumulator. The bistable sign flip-flop FF comprises outputs A and B,,,,, which are connected through an inverter 9 and 10 respectively to outputs S, and 8,. The outputs A,, and B are each connected via a differentiating network D by way of an inverter 11 and 12 respectively to an output E. FIG. 2c illustrates how the result can be read from the accumulator. The outputs A,, B, of the bistable flip-flops of the accumulator are connected to Nands D,,, D,,,, D,,, D,,, D,,,, D,,,. The outputs S, and S of the signalling device S of FIG. 2b are connected to other inputs of said Nands D,,, D,,; S, to D,,,. D,,, D,,, D,,, and S to D,,,, D, D,,, D,,,. The outputs of the pairs of Nands D,,, D,, are interconnected and form the outputs of the read unit.

FIG. 2d shows how the bit values of the binary number c can be cut off from input in the arithmetic member in order to enable to add an additional value I to the result in the accumulator or to subtract it therefrom at the passage of the accumulator through zero. A signal E, inverted by an inverter 1 (originating from the element 0 of FIG. 2a) controls the Nands G G,,... G,,,, to which are applied the bits c c of the second binary number c. If E, 1, the Nands G G, are cut off and hence via the inverter I the signals c 0, are all 0 or E E,,, are all 1. The operation of the arithmetic member shown in FIG. 2 and FIGS. 2a, 2b, 2c and 2d, is explained more fully hereinbelow. Normally up to the maximum capacity of the accumulator a value 0 is present in the last bistable flipflop FF of the accumulator. This means A,, 0 and E I. By means of the Nands N, and N it is ensured that in an addition the bistable sign flip-flop FF is in the state 0 (T l and T' 0) so that A 0 and via Nand 9 S, 1. By this S, l the Nand gates (see FIG. 20) D,,,, D,,, D,,, D,,, are prepared and pass the A,,, A,, A states of the bistable flip-flop of the accumulator. If A, I, there appears after inversion in an inverter 1 a bit value I at the output V,, whereas if A, O, a bit value 0 appears. In subtraction the same applies as long as numbers lower than the result present in the accumulator are subtracted. If in subtracting the accumulator passes the zero position from positive to negative, the following occurs: The bistable flip-flop FF changes its state and A,, becomes I so that 8,, becomes 0. Nand N is prepared during subtractions so that it supplies T 0, as a result of which the bistable sign flip-flop changes its state and A becomes 1 and B becomes 0. The change-over of B from 1 to 0 is transferred via a difierentiating network D and Nand 12 in the form of a signal 0 to the output E. Instead of the output S now the output S, has the signal 1 so that as illustrated in FIG. 2c the outputs B 8,, B,, of the accumulator are connected to the outputs V,,, V,, via Nands D,,,, D,,, D,,,. This means that a negative number is read. The accumulator has passed from positive to negative through the zero position so that an additional binary number 1 has to be subtracted from the result. For this purpose in this embodiment the signal 0 of output E (FIG. 2b) is applied to the elements O and 0 of FIG. 2a. 0 and O may be monostable flip-flops. 0 supplies, due to this O-signal, a signal E after a short time, which signal subsequent to inversion cuts off the Nands G G shown in FIG. 2d and thus produces the binary number to be supplied to the arithmetic member. Immediately thereafler 0 supplies a signal E,, which produces via a differentiating network D a control-signal T for controlling the bistable flip-flop FF Because the subtraction control is still energized, a binary number 1 is then subtracted from the result in the accumulator. If during addition the accumulator passes the zero position from negative to positive, the same occurs, but the bistable flip-flop FF changes vover from 1 to 0, which means that A =0 or B 1. By this B l and the Ad line having a signal 1 (addition), T' receives a 0 signal so that the bistable sign flip-flop changes over and A 0 and B 1. Thus again the A A states of the bistable flip-flops are read (S, l) and via the Nand 11 a O-signal is supplied at the output E. As described above an additional binary number 1 is thus added to the result in the accumulator with the aid of the elements O and C FIG. 3 shows a slight modification of the signalling device S of FIG. 2b. With a sequence of additions and subtractions the state of the bistable sign flip-flop FF is transferred at the beginning I, of a sequence via Nands 13 and 14, prepared by 1,, to a bistable flip-flop F F The latter retains the initial state of flip-flop FF At the termination of a sequence of additions and subtractions at the instant t the actual state of F F is compared via a Nand 15 prepared by t, with that of FF M2 by means of a Nand 16. If the states (herein A and A are equal, no O-signal appears at the output E of gate 16. If the states are unequal, a 0 -signal does appear at the output E so that in dependence upon the state of the bistable sign flip-flop FF an additional binary number 1 is added to or subtracted from the result in the accumulator. It is thus avoided that at each passage of the accumulator through zero an additional value I should be added or subtracted, which means an economy in time. After the termination of a sequence the result is corrected, if necessary. FIG. 4 illustrates how a higher speed of operation can be attained, if it is considered that the actual processing time of an addition (or sub traction) is mainly determined by the change-over times of the bistable flip-flops changing their states. FIG. 4 shows that the output T of the control-device of FIG. 2a and the output of said control-device where the signal A B, (or A A, with subtraction)- I' -n 8,, is produced as the result of a change-over of an ordinally higher preceding bistable flip-flop, are connected to a starting pulse generator Q Q P. The signal (ABJ AAJ F '75,, is formed in the last stage of the control-device by applying the signal via the line 1 (see also FIG. 2a) to a Nand 4105 and the signal ABg/AA to a Nand 4106. These Nands 4105 and 4106 also receive the signal F so that at the combined outputs the signal (AB IAA 5, or, if (AB I AA,) 0, the signal (AB I AA fi f etc. appear. This signal indicates the instant at which the last bistable flip-flop has changed its state. If this last change-over occurs in the last bistable flipflop of the accumulator portion In, this is signalled to the accumulator portion lb by the control-signal T If one of the two signals appears, this means that a new arithmetic operation can start. It is not necessary to wait until a time has elapsed which is equal to the sum of the change-over times of all bistable flip-flops. If there is provided an accumulator portion 1b the transfer of the signal T (in this case T has to be delayed via a network V by a time equal to that required by the portion lb for attaining its final position. The latter may be very soon if a known, so-called synchronous counter is used. The starting pulse generator may comprise a gate P through which a clock pulse is applied through the line C, to a ring counter having stages Q, and Q This clock pulse produces in the portion Q a signal at the line St which serves to prepare (not shown) the second binary number c for an addition (or subtraction) process. The second clock pulse produces in the portion Q, a starting pulse (see FIG. 2a) across the line St,. Thus the adding (subtracting) process is started and a further output of portion Q cuts off the gate P for further clock pulses. When the signal (ABJAAJ-F, or T,, ,(=T,,) appears, the

ring counter is reset and hence the gate P is released and so FIG. 5 finally illustrates what has to be done, if it is desired to perform additions and subtractions in arbitrary order. The potential passage of the accumulator through zero requires steps to avoid that a reset signal for said ring counter Q Q, should be supplied too soon by the appearance of the controlsignal T,,,.,. This step consists in that four Nand gates l7, 18, 19 and 20 are provided. To the gate 17 are connected the adding instruction line, the 8, output of the bistable sign-flip-flop (FF,, see FIG. 2b) and through a difl'erentiating network D the output 21 of a monostable flip-flop OS sewing as a delay circuit, which delays the signal T,, by a time as required for the accumulator portion lb, if any, to attain its final state. In the case of addition and if the state of the accumulator is positive (Ad l and S 1), a signal T, can produce a reset of the ring counter 0,, Q, and hence a new start. The same applies to gate 18, to which are connected the subtraction instruction lines Sbt, the output 8: of the bistable sign flip-flop and also the output 21 of the monostable flip-flop Os. In the case of subtraction and if the state of the accumulator is negative (Sbt l and S l), a signal T, can give rise to a new start.

To gate 19 areconnected the adding instruction line, the output S, of the bistable sign flip-flop and via a differentiating network D the output 22 of a monostable flip-flop Os, serving as a delay circuit delaying the signal T, to an extent such that an end-around carry can be completed at the passage of the accumulator through zero. In the case of addition and when the accumulator is negative a signal T is delayed additionally. If the latter occurs an additional 1 is added to the result (see the foregoing). Then the whole process runs normally. lf no end-around carry occurs, T, becomes available after the delay for actuating a next-following start. The same applies to gate 20 in subtraction when the state of the accumulator is positive. In this embodiment the signal (ABJAAQ-L', F, is, of course, also available and its effect is the same as in the device shown in FIG. 4.

What is claimed is:

1. A binary addition arithmetic member comprising an accumulator receiving a first binary number, the accumulator formed by a plurality of bistable flip-flops having states characterized by 0 and I, an input register for receiving a second binary number, a control-device having inputs to which are connected the outputs of the accumulator and the outputs of the input register, said control-device producing control-signals for setting an adding result in the accumulator so that in order of succession the bistable flip-flops of said accumulator at the consecutive bit places of the accumulator change their states, said state changes starting from a 0-to-1 change-over of a preceding bistable flip-flop, a next-following corresponding bit place of the second binary number has a bit value 1 and for which, starting from a l-to-O change-over of a preceding bistable'flip-ilop a next-following corresponding bit place of the second binary number has a bit value 0, said con trol-device comprising a sensing circuit for sensing the least significant bit place at which said second binary number has a bit value 1, means connecting outputs of said sensing circuit corresponding to the respective bit places of the binary number to the corresponding inputs of said accumulator, means providing a starting pulse from said sensing circuit to said accumulator to cause the bistable flip-flop of the accmulator to change its state which said bistable flip-flop corresponds ordinally to the said least significant bit place where the second binary number has a bit value 1, said controldevice further including a gate circuit coupled to said accumulator, said gate circuit, together with said sensing circuit, satisfying the following logical equation, so that a controlsignal is obtained at an output T, for controlling an i" bistable flip-flop of the accumulator, where T;

K Eli-1 l t 2 H t wherein c c are the bit values of the ordinally consecutive bit places of the second binary number and AA, and AB, represent l-to-O change-overs of the complementary outputs (A 3,) of an i" bistable flip-flop of the accumulator.

2. A binary adding arithmetic member as claimed in claim 1 suitable for adding and subtracting binary numbers in arbitrary order wherein said bistable flip-flops of said accumulator are provided with addition-subtraction control means,

by q, the arithmetic member further comprising a signalling device responsive to the negative-positive passage of said accumulator through zero which provides a further binary number 1 to be added to the result in the accumulator at each subtraction.

5. A binary adding and subtracting arithmetic member as claimed in claim 4, wherein said signalling device comprises a two-way counter which registers the number of times of subtractions and of the negative-positive passages of the accumuwhereby in said logical equation in the case of subtraction A, 10 a through Zero CCLl ng in 8 Series Of additi ns and Subcan be replaced by AB, and AB, by AA the arithmetic member further comprising a signalling device coupled to said accumulator and responsive to the passage of said accumulator as a whole through the zero position, said signalling device comprising a bistable sign flip-flop which provides a further binary number 1 to be subtracted from the result in said accumulator at a passage of the accumulator through zero by subtraction and which provides a further binary number 1 to be added to the result in the accumulator at a passage of the accumulator through zero by an addition from negative to positwe.

3. A binary adding and subtracting arithmetic member as claimed in claim 2, wherein said signalling device comprises an additional bistable flip-flop responsive to the state of said bistable sign flip-flop at the beginning of a sequence of additions and subtractions, the addition or subtraction of said further binary number 1 being performed only after said sequence, when the state of the bistable sign flipflop differs from the state of said additional bistable flip-flop.

4. A binary adding arithmetic member as claimed in claim 1 suitable for adding and subtracting binary numbers in arbitrary order, wherein said input register is provided with a gate circuit for applying, in the case of subtraction, said second binary number in inverted form to said arithmetic member, whereby in the logical equation 0, can be replaced by E, and E,

tractions, the state of said two-way counter afier one such series being added to the result in the accumulator.

6. A binary adding arithmetic member as claimed in claim 1, wherein the output of the control-device for the controlsignal (T from the last stage of the control-device and the output of the control-device for the signal (A B; f 6 c.) produced in the last stage due to an actual change-over of an ordinally higher preceding bistable flip-flop are connected to start means for providing a starting pulse (P, 0,, 0;), which supplies a starting pulse (St after one of said signals has appeared.

7. A binary adding and subtracting arithmetic member as claimed in claim 6, further including a plurality of and-gates, to an input of each of which are connected an output of a bistable sign flip-flop, an adding or subtracting instruction line and the control-signal (T from the last stage of said control-device, the output of said gates coupled to said means providing a starting pulse, said means providing a starting pulse coupled to said accumulator for reactivation at the end of a prior operation, said gates responsive to a coincidence of inputs for passing the control-signal (T from the last stage of said control-device to said means providing a starting pulse, after the passage of the accumulator through zero, when the adding or subtracting process has completely finished. 

1. A binary addition arithmetic member comprising an accumulator receiving a first binary number, the accumulator formed by a plurality of bistable flip-flops having states characterized by 0 and 1, an input register for receiving a second binary number, a control-device having inputs to which are connected the outputs of the accumulator and the outputs of the input register, said control-device producing control-signals for setting an adding result in the accumulator so that in order of succession the bistable flip-flops of said accumulator at the consecutive bit places of the accumulator change their states, said state changes starting from a 0-to-1 change-over of a preceding bistable flipflop, a next-following corresponding bit place of the second binary number has a bit value 1 and for which, starting from a 1to-0 change-over of a preceding bistable flip-flop a nextfollowing corresponding bit place of the second binary number has a bit value 0, said control-device comprising a sensing circuit for sensing the least significant bit place at which said second binary number has a bit value 1, means connecting outputs of said sensing circuit corresponding to the respective bit places of the binary number to the corresponding inputs of said accumulator, means providing a starting pulse from said sensing circuit to said accumulator to cause the bistable flip-flop of the accmulator to change its state which said bistable flip-flop corresponds ordinally to the said least significant bit place where the second binary number has a bit value 1, said controldevice further including a gate circuit coupled to said accumulator, said gate circuit, together with said sensing circuit, satisfying the foLlowing logical equation, so that a control-signal is obtained at an output Ti for controlling an i th bistable flip-flop of the accumulator, where Ti co . c1 ... ci 1 . ci + Delta Ao . c1 ... ci 1 . ci + Delta A1 . c2 ... ci 1 . ci + ... + Delta Ai 2 . ci 1 . ci + Delta Ai 1 . ci Delta Boci 1 .ci + Delta B1 .c2 ... ci 1 .ci + ... + Delta Bi 2 .ci 1 .ci + Delta Bi 1 ci wherein co, c1, ... are the bit values of the ordinally consecutive bit places of the second binary number and Delta Ai and Delta Bi represent 1-to-0 change-overs of the complementary outputs (Ai, Bi) of an ith bistable flip-flop of the accumulator.
 2. A binary adding arithmetic member as claimed in claim 1 suitable for adding and subtracting binary numbers in arbitrary order wherein said bistable flip-flops of said accumulator are provided with addition-subtraction control means, whereby in said logical equation in the case of subtraction Ai can be replaced by Delta Bi and Delta Bi by Delta Ai, the arithmetic member further comprising a signalling device coupled to said accumulator and responsive to the passage of said accumulator as a whole through the zero position, said signalling device comprising a bistable sign flip-flop which provides a further binary number 1 to be subtracted from the result in said accumulator at a passage of the accumulator through zero by subtraction and which provides a further binary number 1 to be added to the result in the accumulator at a passage of the accumulator through zero by an addition from negative to positive.
 3. A binary adding and subtracting arithmetic member as claimed in claim 2, wherein said signalling device comprises an additional bistable flip-flop responsive to the state of said bistable sign flip-flop at the beginning of a sequence of additions and subtractions, the addition or subtraction of said further binary number 1 being performed only after said sequence, when the state of the bistable sign flip-flop differs from the state of said additional bistable flip-flop.
 4. A binary adding arithmetic member as claimed in claim 1 suitable for adding and subtracting binary numbers in arbitrary order, wherein said input register is provided with a gate circuit for applying, in the case of subtraction, said second binary number in inverted form to said arithmetic member, whereby in the logical equation ci can be replaced by ci and ci by ci, the arithmetic member further comprising a signalling device responsive to the negative-positive passage of said accumulator through zero which provides a further binary number 1 to be added to the result in the accumulator at each subtraction.
 5. A binary adding and subtracting arithmetic member as claimed in claim 4, wherein said signalling device comprises a two-way counter which registers the number of times of subtractions and of the negative-positive passages of the accumulator through zero occuring in a series of additions and subtractions, the state of said two-way counter after one such series being added to the result in the accumulator.
 6. A binary adding arithmetic member as claimed in claim 1, wherein the output of the control-device for the control-signal (Tn 1) from the last stage of the control-device and the output of the control-device for the signal ( Delta Bi. ci
 1. ci 2 ... cn) produced in the last stage due to an actual change-over of an ordinally higher preceding bistable flip-flop are connected to start means for providing a starting pulse (P, Q1, Q2), which supplies a starting pulse (St1) after one of said signals has appeared.
 7. A binary adding and subtracting arithmetic member as claimed in claim 6, further including a plurality of and-gates, to an input of each of which are connected an output of a bistable sign flip-flop, an adding or subtracting instruction line and the control-signal (Tn 1) from the last stage of said control-device, the output of said gates coupled to said means providing a starting pulse, said means providing a starting pulse coupled to said accumulator for reactivation at the end of a prior operation, said gates responsive to a coincidence of inputs for passing the control-signal (Tn 1) from the last stage of said control-device to said means providing a starting pulse, after the passage of the accumulator through zero, when the adding or subtracting process has completely finished. 